Conventionally, with regard to nonvolatile semiconductor memory devices such as a flash memory and the like, it is known that when data writing is selectively performed to a selected memory cell, a write-disturb phenomenon occurs in which a memory cell that is not selected is affected. In particular, along with progress in miniaturization, the write-disturb phenomenon is becoming evident as a problem.
In Patent Document 1, there is a description of a conventional flash memory device having a write-disturb prevention function. FIG. 3 is a block diagram of the overall conventional flash memory device described in Patent Document 1 where the device includes row decoder and word line driver 20, source decoder and source line driver 30, control circuit 60, and current mirror circuit 70. Bias voltage VBIAS is input to input driver 40 and control circuit 60. Input driver 40 also receives input data DIN1 to DINn. According to Patent Document 1, at a time of writing (programming) data, among a plurality of word lines (WL1 to WL2m) of a flash memory array 10, approximately 1 V is given to a selected word line and Vss are given to nonselected word lines. In the same way, there is a description of giving, among a plurality of source lines (SL1 to SLm), Vpp (approximately 10 V) to a selected source line and Vss to nonselected source lines, and among a plurality of bit lines (BL1 to BLn), giving approximately 0.4 V to a selected bit line and Vcc to nonselected bit lines, and performing writing (programming). With regard to the selection of bit lines, selection of a plurality or bit lines at the same time is possible, and writing to a plurality of memory cells having a common word line at the same time is possible.
The flash memory array 10 is configured as in a block diagram shown in FIG. 4, and when writing (programming) is performed to a memory cell 11, a current Ip flows in a route of: source line SL1 to memory cell 11 and bit line BL1, and writing (programming) is performed with regard to the memory cell 11. When writing is performed with regard to the memory cell 11, a memory cell 12 having the source line SL1 and the bit line BL1 in common may also receive an effect of the writing. This is a write-disturb effect. In particular, since current flowing from a source line differs according to the number of memory cells performing writing at the same time, the voltage Vpp of the source line also receives an effect. In particular, in a case where the number of memory cells performing writing at the same time is small, since the voltage Vpp of the source line is a high voltage, the write-disturb effect easily occurs.
In Patent Document 1, in order to prevent this write-disturb occurrence, a program current compensation circuit 100 (FIG. 3) is provided, and in a case where the number of memory cells performing writing at the same time is small and the current flowing in the flash memory cell array 10 is small, by a current flowing in the program current compensation circuit 100 instead of the flash memory cell array 10, according to the number of memory cells performing writing at the same time, load on a program voltage generation circuit 50, which generates the voltage Vpp of the source line, is always equal.
FIG. 5 is a block diagram of the program current compensation circuit 100 described in Patent Document 1. The circuit 100 includes transistors MN5, MN6, MP3, MP2, MN31, MN32, MN41, MN3n and MN4n, as well as nodes N3, N5, N41, N42 and N4n, arranged as shown in FIG. 5. According to write data DIN1 to DINn, current flowing at a current source of a current mirror circuit is gradually changed, and by this current flowing from a power supply Vpp of a source line by current mirror circuits 68 and 70, the current flowing in the source line is always constant, independent of the number of memory cells performing writing at the same time, and the occurrence of a write-disturb effect is prevented.
[Patent Document 1]
    JP Patent Kokai Publication No. JP2007-193936A, which corresponds to US Patent Publication No. US2007/0171727A1.